maisМоделирование и анализ информационных системModeling and Analysis of Information Systems1818-10152313-5417Yaroslavl State University10.18255/1818-1015-2022-1-60-72mais-1608Research ArticleTheory of ComputingМетоды преобразования параллелизма в процессе высокоуровневого синтеза СБИСMethods for Change Parallelism in Process of High-level VLSI Synthesishttps://orcid.org/0000-0002-3069-9102РыженкоИгорь НиколаевичRyzhenkoIgor Nikolaevichodgi.krs@gmail.comhttps://orcid.org/0000-0002-2459-6414НепомнящийОлег ВладимировичNepomnyaschyOleg Vladimirovich2955005@gmail.comhttps://orcid.org/0000-0002-5487-0699ЛегаловАлександр ИвановичLegalovAleksandr Ivanovichalegalov@hse.ruhttps://orcid.org/0000-0002-7883-5804ШайдуровВладимир ВикторовичShaidurovVladimir Viktorovichshaidurov04@mail.ruСибирский Федеральный УниверситетРоссияSiberian Federal UniversityRussian FederationНациональный исследовательский университет “Высшая школа экономики”РоссияHigher School of EconomicsRussian FederationФГБНУ Федеральный исследовательский центр “Красноярский научный центр Сибирского отделения Российской академии наук”РоссияKrasnoyarsk Science Centre of the Siberian Branch of Russian Academy of ScienceRussian Federation2022170320222916072Copyright © Рыженко И.Н., Непомнящий О.В., Легалов А.И., Шайдуров В.В., 20222022Рыженко И.Н., Непомнящий О.В., Легалов А.И., Шайдуров В.В.Ryzhenko I.N., Nepomnyaschy O.V., Legalov A.I., Shaidurov V.V.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://www.mais-journal.ru/jour/article/view/1608

Предложены методы повышения эффективности разработки СБИС на основе метода архитектурно-независимого проектирования. Рассмотрен маршрут высокоуровневого синтеза СБИС. Изложен принцип построения аппаратной модели СБИС на основе функционально-потоковой парадигмы программирования.Представлены результаты разработки методов и алгоритмов трансформации, функционально-потоковых параллельных программ в программы на языках описания аппаратуры, обеспечивающих поддержку процесса проектирования цифровых однокристальных систем. Рассмотрены принципы оценки и выделены классы ресурсов, требуемых для анализа проектных решений. Введены коэффициенты редукции и методики их расчета по каждому классу ресурсов. Предложен алгоритм расчета коэффициентов редукции и оценки требуемых ресурсов. Предложен алгоритм преобразования параллелизма с учетом заданных ограничений целевой платформы. Разработан механизм обмена метриками с архитектурно-зависимым уровнем. Приведены примеры редукции параллелизма для платформы ПЛИС и практическая реализация тестовых алгоритмов БПФ в базисе ПЛИС Virtex® UltraScale. Разработанные методы и алгоритмы позволяют использовать метод архитектурно-независимого синтеза для переноса проектов СБИС на различные архитектуры с помощью изменения параллелизма схемы и эквивалентных преобразований параллельных программ. Предложенный подход обеспечивает множество вариантов аппаратных решений для реализации на различных целевых платформах.

In this paper methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated.The results of the development of methods and algorithms for transformation functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the analysis of design solutions are identified. Reduction coefficients and methods of their calculation for each resource class have been introduced. An algorithm for calculating the reduction coefficients and estimating the required resources is proposed. An algorithm for converting parallelism is proposed, taking into account the specified constraints of the target platform. A mechanism for the exchange of metrics with an architecture-dependent level has been developed. Examples of parallelism reduction for the FPGA platform and practical implementation of FFT algorithms in the Virtex® UltraScale FPGA basis are given. The developed methods and algorithms make it possible to use the method of architecture-independent synthesis for transferring VLSI projects to various architectures by changing the parallelism of the circuit and equivalent transformations of parallel programs. The proposed approach provides many options for hardware solutions for implementation on various target platforms.

параллельные вычисленияпотоки данныхфункционально-потоковое параллельное программированиецифровая интегральная схемавысокоуровневый синтезparallel computingdataflowfunctional programminghigh-level synthesisVLSIReferencesT. M. Bhatt and D. McCain, “Matlab as a Development Environment for FPGA Design”, in Design Automation Conference, Proceedings 42nd, 2005, pp. 607-610.T. M. Bhatt and D. McCain, “Matlab as a Development Environment for FPGA Design”, in Design Automation Conference, Proceedings 42nd, 2005, pp. 607-610.L. Lavagno, I. L. Markov, G. Martin, and L. K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing. CRC Press, 2017.L. Lavagno, I. L. Markov, G. Martin, and L. K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing. CRC Press, 2017.Z. Navabi, System-Level Design and Modeling: ESL Using C/C++, SystemC and TLM-2.0. Springer, 2015.Z. Navabi, System-Level Design and Modeling: ESL Using C/C++, SystemC and TLM-2.0. Springer, 2015.Vivado Design Suite User Guide. High-Level Synthesis. UG902. [Online]. Available: http://www.xilinx.com/support/documentation/sw_manuals/xilinx20181/ug902-vivado-high-level-synthesis.pdf.Vivado Design Suite User Guide. High-Level Synthesis. UG902. [Online]. Available: http://www.xilinx.com/support/documentation/sw_manuals/xilinx20181/ug902-vivado-high-level-synthesis.pdf.Z. Yuan, Y. Ma, J. Bian, and K. Zhao, “Automatic enhanced CDFG generation based on runtime instrumentation”, in IEEE 17th International Conference on, 2013, pp. 92-97.Z. Yuan, Y. Ma, J. Bian, and K. Zhao, “Automatic enhanced CDFG generation based on runtime instrumentation”, in IEEE 17th International Conference on, 2013, pp. 92-97.G. Bosilca, A. Bouteiller, A. Danalis, M. Faverge, T. He´rault, and J. J. Dongarra, “PaRSEC: Exploiting Heterogeneity to Enhance Scalability”, IEEE Computing in Science and Engineering, vol. 15, no. 6, pp. 36-45, 2013.G. Bosilca, A. Bouteiller, A. Danalis, M. Faverge, T. He´rault, and J. J. Dongarra, “PaRSEC: Exploiting Heterogeneity to Enhance Scalability”, IEEE Computing in Science and Engineering, vol. 15, no. 6, pp. 36-45, 2013.A. Danalis, G. Bosilca, A. Bouteiller, T. Herault, and J. Dongarra, “PTG: An Abstraction for Unhindered Parallelism”, in Proceedings of the Fourth International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, 2014, pp. 21-30.A. Danalis, G. Bosilca, A. Bouteiller, T. Herault, and J. Dongarra, “PTG: An Abstraction for Unhindered Parallelism”, in Proceedings of the Fourth International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, 2014, pp. 21-30.I. I. Levin and A. I. Dordopulo, “Resource-independent programming of hybrid reconfigurable computer systems”, in Proceedings of Russian Supercomputing Days, 2017, pp. 714-723.I. I. Levin and A. I. Dordopulo, “Resource-independent programming of hybrid reconfigurable computer systems”, in Proceedings of Russian Supercomputing Days, 2017, pp. 714-723.I. I. Levin, A. I. Dordopulo, I. V. Pisarenko, and A. K. Melnikov, “An approach to architecture-independent programming of computing systems based on the aspect-oriented Set@l language”, Proceedings of the Southern Federal University. Technical sciences, vol. 197, no. 3, pp. 46-57, 2018.I. I. Levin, A. I. Dordopulo, I. V. Pisarenko, and A. K. Melnikov, “An approach to architecture-independent programming of computing systems based on the aspect-oriented Set@l language”, Proceedings of the Southern Federal University. Technical sciences, vol. 197, no. 3, pp. 46-57, 2018.O. V. Nepomnyaschy, I. N. Ryzhenko, and A. I. Legalov, “The method of architecturally independent high-level synthesis of VLSI”, Proceedings of the Southern Federal University. Technical sciences, vol. 202, no. 8, pp. 38-47, 2018.O. V. Nepomnyaschy, I. N. Ryzhenko, and A. I. Legalov, “The method of architecturally independent high-level synthesis of VLSI”, Proceedings of the Southern Federal University. Technical sciences, vol. 202, no. 8, pp. 38-47, 2018.A. I. Legalov, “Functional language for creation of architectural independent parallel programmes”, Computational Technologies, vol. 10, no. 1, pp. 71-89, 2005.A. I. Legalov, “Functional language for creation of architectural independent parallel programmes”, Computational Technologies, vol. 10, no. 1, pp. 71-89, 2005.A. I. Legalov, V. S. Vasilyev, I. V. Matkovskii, and M. S. Ushakova, “A toolkit for the development of data-driven functional parallel programmes”, in International Conference on Parallel Computational Technologies, Springer, 2018, pp. 16-30.A. I. Legalov, V. S. Vasilyev, I. V. Matkovskii, and M. S. Ushakova, “A toolkit for the development of data-driven functional parallel programmes”, in International Conference on Parallel Computational Technologies, Springer, 2018, pp. 16-30.V. Vasilev, A. I. Legalov, and S. V. Zykov, “The System for Transforming the Code of Dataflow Programs into Imperative”, Modeling and Analysis of Information Systems, vol. 28, no. 2, pp. 198-214, 2021.V. Vasilev, A. I. Legalov, and S. V. Zykov, “The System for Transforming the Code of Dataflow Programs into Imperative”, Modeling and Analysis of Information Systems, vol. 28, no. 2, pp. 198-214, 2021.O. V. Nepomnyaschy and I. N. Ryzhenko, “The method of high-level synthesis and software toolkit for description algorithm of VLSI”, Software Engineering, vol. 11, no. 1, pp. 34-39, 2020.O. V. Nepomnyaschy and I. N. Ryzhenko, “The method of high-level synthesis and software toolkit for description algorithm of VLSI”, Software Engineering, vol. 11, no. 1, pp. 34-39, 2020.Vivado Design Suite User Guide. Using the Vivado IDE UG893. [Online]. Available: https://www.xilinx.com/support/documentation/swmanuals/xilinx2020_2/ug893-vivado-ide.pdf.Vivado Design Suite User Guide. Using the Vivado IDE UG893. [Online]. Available: https://www.xilinx.com/support/documentation/swmanuals/xilinx2020_2/ug893-vivado-ide.pdf.

The authors declare that there are no conflicts of interest present.