Methods for Change Parallelism in Process of High-level VLSI Synthesis
Igor Nikolaevich Ryzhenko,
Oleg Vladimirovich Nepomnyaschy,
Aleksandr Ivanovich Legalov,
Vladimir Viktorovich Shaidurov https://doi.org/10.18255/1818-1015-2022-1-60-72
Abstract
In this paper methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated.The results of the development of methods and algorithms for transformation functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the analysis of design solutions are identified. Reduction coefficients and methods of their calculation for each resource class have been introduced. An algorithm for calculating the reduction coefficients and estimating the required resources is proposed. An algorithm for converting parallelism is proposed, taking into account the specified constraints of the target platform. A mechanism for the exchange of metrics with an architecture-dependent level has been developed. Examples of parallelism reduction for the FPGA platform and practical implementation of FFT algorithms in the Virtex® UltraScale FPGA basis are given. The developed methods and algorithms make it possible to use the method of architecture-independent synthesis for transferring VLSI projects to various architectures by changing the parallelism of the circuit and equivalent transformations of parallel programs. The proposed approach provides many options for hardware solutions for implementation on various target platforms.
About the Authors
Igor Nikolaevich Ryzhenko
Siberian Federal University
Russian Federation
Russian Federation
Oleg Vladimirovich Nepomnyaschy
Siberian Federal University
Russian Federation
Russian Federation
Aleksandr Ivanovich Legalov
Higher School of Economics
Russian Federation
Russian Federation
Vladimir Viktorovich Shaidurov
Krasnoyarsk Science Centre of the Siberian Branch of Russian Academy of Science
Russian Federation
Russian Federation
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Review
For citations:
Ryzhenko I.N., Nepomnyaschy O.V., Legalov A.I., Shaidurov V.V. Methods for Change Parallelism in Process of High-level VLSI Synthesis. Modeling and Analysis of Information Systems. 2022;29(1):60-72. (In Russ.) https://doi.org/10.18255/1818-1015-2022-1-60-72
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