On Verification of PLC-Programs Written in the LD-Language
https://doi.org/10.18255/1818-1015-2012-2-138-144
Abstract
We discuss some questions connected with the construction of a technology of analysing correctness of Programmable Logic Controller programs. We consider an example of modeling and automated verification of PLC-programs written in the Ladder Diagram language (including timed function blocks) of the IEC 61131-3 standard. We use the Cadence SMV for symbolic model checking. Program properties are written in the linear-time temporal logic LTL.
About the Authors
E. V. Kuzmin
Ярославский государственный университет им. П.Г. Демидова
Russian Federation
д-р физ.-мат. наук, доцент
Russian Federation
д-р физ.-мат. наук, доцент
V. A. Sokolov
Ярославский государственный университет им. П.Г. Демидова
Russian Federation
д-р физ.-мат. наук, профессор
Russian Federation
д-р физ.-мат. наук, профессор
References
1. Грис Д. Наука программирования. Пер. с англ. М.: Мир, 1984. 416 с.
2. Кларк Э. М., Грамберг О., Пелед Д. Верификация моделей программ: Model Checking. Пер. с англ. М.: МЦНМО, 2002. 416 с.
3. Парр Э. Программируемые контроллеры: руководство для инженера. М.: БИНОМ. Лаборатория знаний, 2007. 516 с.
4. Петров И. В. Программируемые контроллеры. Стандартные языки и приемы прикладного проектирования. М.: СОЛОН-Пресс, 2004. 256 с.
5. Canet G., Couffin S., Lesage J.-J., Petit A., Schnoebelen Ph. Towards the Automatic Verification of PLC Programs Written in Instruction List // Proceedings of the IEEE International Conference on Systems, Man and Cybernetics (SMC-2000), Argos Press, 2000. P. 2449-2454.
6. CoDeSys. Controller Development System. http://www.3s-software.com/
7. Pavlovic O., Pinger R., Kollmann M. Automation of Formal Verification of PLC Programs Written in IL // Proceedings of 4th International Verification Workshop (VERIFY’07), Bremen, Germany, 2007. P. 152-163.
8. Rossi O., Schnoebelen Ph. Formal Modeling of Timed Function Blocks for the Automatic Verification of Ladder Diagram Programs // Proceedings of the 4th International Conference on Automation of Mixed Processes: Hybrid Dynamic Systems (ADPM-2000), Shaker Verlag, 2000. P. 177-182.
9. SMV. The Cadence SMV Model Checker. http://www.kenmcmil.com/smv.html
Review
For citations:
Kuzmin E.V., Sokolov V.A. On Verification of PLC-Programs Written in the LD-Language. Modeling and Analysis of Information Systems. 2012;19(2):138-144. (In Russ.) https://doi.org/10.18255/1818-1015-2012-2-138-144
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